Power devices are electronic components designed to be tolerant of the high currents and voltages that are present in power applications such as motion control, air bag deployment, and automotive fuel injector drivers. The power lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect-transistor (FET) device, referred to herein as a power LDMOS device, is becoming increasingly popular for power applications. As power technologies develop, power applications require smaller and smaller power LDMOS devices. Power LDMOS devices in deep sub-micrometer (sub-micron) technologies are difficult to design, however, in part due to limited epitaxial layer thickness and limited thermal budget. Furthermore, power LDMOS devices must be designed to operate in a “high-side configuration,” which is a configuration in which all the device terminals are level shifted with respect to the substrate potential. A device that may be operated in a high-side configuration is said to be “high-side capable.” High-side capable power LDMOS devices are designed to prevent a direct punch-through path from a body region of the power LDMOS device to an underlying, heavily doped substrate. Limited epitaxial layer thicknesses make this high-side capability problematic as well because the punch-through problem becomes worse as the epitaxial layer thickness decreases.
Existing technology attempts to satisfy the high breakdown voltage requirement by utilizing a power LDMOS device having a reduced surface field (RESURF) structure. A power LDMOS device having a RESURF structure comprises a first semiconductor region, which serves as a RESURF region, having one conductivity type and a second semiconductor region, which serves as a drift region, having a different conductivity type. The RESURF region depletes the drift region, thus reducing the electric field in the drift region and allowing a higher breakdown voltage for the power LDMOS device. The RESURF structure just described is referred to herein as a “single RESURF” structure.
A “double RESURF” structure, on the other hand, comprises first and third semiconductor regions, which serve as dual RESURF regions, having one conductivity type and a second semiconductor region, which serves as a drift region, having a different conductivity type. In the double RESURF structure, each of the dual RESURF regions deplete the drift region, thus reducing the electric field in the drift region to a greater degree than is possible with a single RESURF structure. A transistor, including power LDMOS devices and bipolar transistors, having a single or double RESURF structure, will be referred to herein as a “RESURF transistor.”
Typical RESURF transistors have a low punch-through voltage between the body region and the heavily doped substrate and hence are not high-side capable. Attempts to increase the punch-through voltage have introduced further problems. For example, ion implanted regions electrically shorted to the drain or source terminals have been formed below the body region to reduce the punch-through problem, but such regions negatively impact breakdown voltage and specific on-resistance (Rdson). For example, increasing N-type doping in the ion implanted regions under a P-type body region in order to absorb more of the electric field in the P-type body region reduces breakdown voltage and increases Rdson. Therefore, a need exists for a RESURF transistor that achieves high breakdown voltage without introducing additional process complexity or negatively impacting Rdson.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures denote the same elements.
The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The terms “left,” “right,” “front,” “back,” “top,” “bottom,”“over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner.